1.3 Control Loop Design Strategy

In any switching converter, control loop design fundamentally involves the strategic placement of poles and zeros to shape the loop gain response across frequency. Each pole and zero directly influences the gain slope and phase behavior of the system, thereby determining stability and dynamic performance. Poles tend to introduce phase lag and reduce stability margin, while zeros provide phase boost and help counteract the effects of dominant poles, such as the double pole introduced by the output LC filter. By carefully selecting the locations of these poles and zeros, the designer can control key parameters such as crossover frequency, phase margin, and transient response.

In ACOT control, this principle remains the same; however, instead of using a traditional error amplifier and compensation network, the placement of poles and zeros is primarily governed by the ripple injection and feedback components. As a result, ACOT control loop design can be effectively viewed as a structured process of shaping the frequency response through appropriate selection of R_INJ, C_INJ and C_FF to achieve the desired stability and performance.

The control loop design strategy for ACOT control focuses on shaping the loop gain profile through proper placement of poles and zeros to ensure stability and optimal transient performance. As illustrated in Figure 1-2, the red curve represents the effect of the output LC filter, which introduces a double pole at ${\mathrm{\omega }}_{\mathrm{P}}=\frac{1}{\sqrt{{\mathrm{LC}}_{\mathrm{OUT}}}}$.

This results in a steep –40 dB/decade slope, causing significant phase lag. If left uncompensated, this would make the system unstable. To counteract this, zeros are introduced through the ripple injection and feedback networks. The first zero (Z1), visible as the flattening of the black curve in the mid-frequency region, is placed around $\frac{{\mathrm{F}}_{\mathrm{LC}}}{10}$ to $\frac{{\mathrm{F}}_{\mathrm{LC}}}{20}$ to reduce phase lag and improve mid-frequency response.

The second zero (Z2), which causes an upward trend in the black curve near crossover, is positioned closer to the crossover frequency to provide additional phase boost and ensure sufficient phase margin, typically at least 60°. The resulting overall loop gain (shown in blue) combines these effects, transitioning from the steep –40 dB/decade slope to a more manageable –20 dB/decade slope (green region) near the crossover frequency F_C, where the gain crosses 0 dB. This controlled shaping of the gain profile ensures stable operation while maintaining fast transient response.

It is important to note that, in this analysis, the output capacitor ESR zero is not explicitly considered. This is because the discussion is focused on the Type 3 ripple injection scheme, which is typically used in designs employing very low-ESR output capacitors, such as MLCCs. In such cases, the ESR zero occurs at a very high frequency, often well beyond the crossover frequency and the region of interest for control loop design.

As a result, it does not provide any meaningful phase boost in the operating bandwidth and can be safely neglected for the purpose of loop analysis. This assumption further reinforces the need for introducing zeros through the ripple injection and feed-forward networks, as they become the primary means of compensating the phase lag introduced by the output LC double pole.