12.2 JTAG_TCK on IOSET 4 pin has a wrong configuration after boot

The JTAG_TCK signal on IOSET 4 shares its pin (PA22) with the clock signal of the following boot memory interfaces: SDMMC1, SPI1 IOSET 2, QSPI 0 IOSET 3.

If JTAG IOSET 4 is selected by the user as JTAG debug port in the Boot Configuration Word, and if the ROM Code boots, or tries to boot, on any of the external memory interfaces stated above, the JTAG clock pin (TCK) is reset at its default mode (PIO) at the end of the ROM Code execution.

This occurs as soon as EXT_MEM_BOOT_ENABLE is set.

Work around

Do not select or disable external memory boot interface SDMMC1, SPI1 IOSET 2 or QSPI0 IOSET 3. However, if using one of these boot interfaces is required, reconfigure the PA22 pin in JTAG TCK IOSET 4 mode in the bootstrap or application.