1 Silicon Issue Summary
| Module | Item/Feature | Summary |
|---|---|---|
| Power Supply | VDDSDMMC power supply over-consumption | Over-consumption on VDDSDMMC power supply |
| FLEXCOM | FLEXCOM SMBUS alert | FLEXCOM SMBUS alert signalling is not functional |
| GMAC | Timestamps and PTP packets | Bad association of timestamps and PTP packets |
| GMAC | Screening registers not working | Screening registers (GMAC_ST1RPQx and GMAC_ST2RPQx) not working |
| I2SC | I2SC sent data | I2SC first sent data corrupted |
| MCAN(1) | CRC | Flexible data rate feature does not support CRC |
| MCAN(1) | MCAN_IR.MRAF interrupt | Needless activation of interrupt MCAN_IR.MRAF |
| MCAN(2) | Bus Integration state | Return of receiver from Bus Integration state after Protocol Exception Event |
| MCAN(2) | Message RAM/RAM Arbiter | Message RAM/RAM Arbiter not responding in time |
| MCAN(2) | Frame receiving | Data loss (payload) in case storage of a received frame has not completed until end of EOF field is reached |
| MCAN(1) | Edge filtering | Edge filtering causes mis-synchronization when falling edge at Rx input pin coincides with end of integration phase |
| MCAN(2) | MCAN_NBTP.NTSEG2 | Configuration of MCAN_NBTP.NTSEG2 = ’0’ not allowed |
| MCAN(2) | DAR mode | Retransmission in DAR mode due to lost arbitration at the first two identifier bits |
| MCAN(2) | Tx FIFO message | Tx FIFO message sequence inversion |
| MCAN(2) | HPM interrupt | Unexpected High Priority Message (HPM) interrupt |
| MCAN(2) | Transmitted message | Issue message transmitted with wrong arbitration and control fields |
| MCAN(2) | Debug message handling state machine not reset |
Debug message handling state machine not reset to Idle state when CCCR.INIT is set |
| MCAN(1) | Frame transmitted despite cancellation | Frame transmitted despite confirmed transmit cancellation for CAN-FD messages with more than 8 data bytes |
| PMC | PMC_MCKR.PRES field | Change of the field PMC_MCKR.PRES is not allowed if Master/Processor Clock Prescaler frequency is too high |
| PTC | Wrong pull-up value on PD[18:3] during reset | Incorrect pull-up value |
| PWM | Fault Protection to Hi-Z for PWMx output | Fault Protection to Hi-Z for PWMx output is not functional |
| QSPI | DLYCS delay | QSPI hangs with long DLYCS |
| RTC | RTC_SR.TDERR flag | RTC_SR.TDERR flag is stuck at 0 |
| RTC | Truncated read access to RTC_TIMALR (UTC_MODE) | Read access truncated to the first 24 bits for register RTC_TIMALR (UTC_MODE) |
| ROM Code | UART connection to SAM-BA Monitor | UART blocks USB connection to SAM-BA Monitor |
| ROM Code | JTAG_TCK | JTAG_TCK on IOSET 4 pin has a wrong configuration after boot |
| ROM Code | Secure Boot Mode: AES-RSA X.509 Certificate Serial Number Length Limit | The length of serial numbers is limited to 16 bytes by the ROM code. |
| SDMMC | Software 'Reset For all' command | Software 'Reset For all' command may not execute properly |
| SDMMC | Sampling clock tuning procedure | Sampling clock tuning procedure may freeze |
| SDMMC | SDMMC I/O calibration does not work | The impedance calibration mechanism for the SDMMC I/Os does not work |
| SFC | Fuse matrix programming | Fuse matrix programming requires a main clock (MAINCK) frequency between 10 and 15 MHz |
| SFC | Fuse matrix read | Fuse matrix read requires a main clock (MAINCK) frequency below 28 MHz |
| SSC | TD output | Unexpected delay on TD output |
| TWIHS | Clear command | The TWI/TWIHS Clear command does not work |
| WDT | Restart command | Restart command of WDT may reset the DDR controller |
Note:
- This erratum is not relevant for CAN 2.0.
- This erratum is applicable for CAN 2.0.