41.5.2.1 Initialization
- Configure the clock source for CLK_TRNG_APB in the Main Clock Controller (MCLK) and
enable the clock by writing a ‘1’ to the TRNG bit in the APB Mask register of the
MCLK.
- Optional: Enable the output event by writing a ‘1’ to the EVCTRL.DATARDYEO bit.
- Optional: Enable the TRNG to Run in Standby Sleep mode by writing a ‘1’ to CTRLA.RUNSTDBY.
- Enable the TRNG operation by writing a ‘1’ to CTRLA.ENABLE. Note: A delay between TRNG Enable (CTRLA.ENABLE = 1) and the first random number read is required. Refer to the TRNG Electrical Specifications.
The following register is enable-protected, meaning that it can only be written when the TRNG is disabled (CTRLA.ENABLE = 0): Event Control register (EVCTRL)
Enable-protection is denoted by the Enable-Protected property in the register description.