27.6.19 Channel Control B

This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).

Name:	CHCTRLB
Offset:	0x44
Reset:	0x00000000
Property:	PAC Write-Protection, Enable-Protected


Bit	31	30	29	28	27	26	25	24
							CMD[1:0]
Access							R/W	R/W
Reset							0	0


Bit	23	22	21	20	19	18	17	16
	TRIGACT[1:0]
Access	R/W	R/W
Reset	0	0


Bit	15	14	13	12	11	10	9	8
			TRIGSRC[5:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
		LVL[1:0]		EVOE	EVIE	EVACT[2:0]
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0

Bits 25:24 – CMD[1:0] Software Command

These bits define the software commands. Refer to Channel Suspend and Channel Resume and Next Suspend Skip.

These bits are not enable-protected.


Value	Name	Description
0x0	NOACT	No action
0x1	SUSPEND	Channel suspend operation
0x2	RESUME	Channel resume operation
0x3	-	Reserved

Bits 23:22 – TRIGACT[1:0] Trigger Action

These bits define the trigger action used for a transfer.


Value	Name	Description
0x0	BLOCK	One trigger required for each block transfer
0x1	-	Reserved
0x2	BEAT	One trigger required for each beat transfer
0x3	TRANSACTION	One trigger required for each transaction

Bits 13:8 – TRIGSRC[5:0] Trigger Source

These bits define the peripheral trigger which is source of the transfer. For additional information on trigger selection and trigger modes, refer to Transfer Triggers and Actions and CHCTRLB.TRIGACT.

Refer to the Peripheral Dependencies table for finding out the value corresponding to each module trigger source.

Important: Refer to the Configuration Summary for the list of peripherals and peripheral instances present in each variant.

Bits 6:5 – LVL[1:0] Channel Arbitration Level

These bits define the arbitration level used for the DMA channel, where a high level has priority over a low level. For additional information on arbitration schemes, refer to the Arbitration.

These bits are not enable-protected.


Value	Name	Description
0x0	LVL0	Channel Priority Level 0
0x1	LVL1	Channel Priority Level 1
0x2	LVL2	Channel Priority Level 2
0x3	LVL3	Channel Priority Level 3

Bit 4 – EVOE Channel Event Output Enable

This bit indicates if the Channel event generation is enabled. The event will be generated for every condition defined in the descriptor Event Output Selection (BTCTRL.EVOSEL).

This bit is available only for the 8 least significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details.

Value	Description
0	Channel event generation is disabled.
1	Channel event generation is enabled.

Bit 3 – EVIE Channel Event Input Enable

This bit is available only for the 8 least significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details.

Value	Description
0	Channel event action will not be executed on any incoming event.
1	Channel event action will be executed on any incoming event.

Bits 2:0 – EVACT[2:0] Event Input Action

These bits define the event input action, as shown below. The action is executed only if the corresponding EVIE bit in the CHCTRLB register of the channel is set.

These bits are available only for the 8 least significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details.


Value	Name	Description
0x0	NOACT	No action
0x1	TRIG	Normal Transfer and Conditional Transfer on Strobe trigger
0x2	CTRIG	Conditional transfer trigger
0x3	CBLOCK	Conditional block transfer
0x4	SUSPEND	Channel suspend operation
0x5	RESUME	Channel resume operation
0x6	SSKIP	Skip next block suspend action
0x7	-	Reserved