9.1 Clocks Distribution

The PIC32CM LE00/LS00/LS60 device clock system is composed of the following:

  • Clock sources (CLK_XXX), which are controlled by the OSCCTRL and OSC32KCTRL peripherals.
  • The Generic Clock Controller (GCLK), which generates and controls the asynchronous clocks of the device (GCLK_XXX):
    • The Generic Clock Generators are programmable prescalers that can use any of the clock sources as a time base.
    • The Peripheral Channels select their generic clock from the different GCLK generators to clock their associated peripherals.
  • The Main Clock Controller (MCLK), which generates and controls the synchronous clocks of the device:
    • This includes the CPU, bus clocks (APB, AHB), and the user interfaces of the peripherals.
Figure 9-1. Clocks Distribution

The following is an example using the FDPPL96M as clock source, where:

  • The Generic Clock Generator 0 provides the Main Clock source (48 MHz)
  • The Generic Clock Generator 1 provides a lower clock to the peripheral (12 MHz)
Figure 9-2. 48 MHz Clocks System Example (Simplified)
Note: As the CPU and peripherals can be in different clock domains, that is, they are clocked from different clock sources and with different clock speeds, some peripheral accesses by the CPU must synchronized. In this case the peripheral includes a Synchronization Busy (SYNCBUSY) register that can be used to check if a sync operation is in progress. For a general description, refer to the Registers Synchronization.