11.1.1 Cortex-M23 Configuration
The following table provides the Arm Cortex-M23 processor configuration.
| Features | PIC32CM LE00 Implementation | PIC32CM LS00/LS60 Implementation |
|---|---|---|
| Memory Protection Unit (MPU) | One MPU with 12 regions | Two MPUs with 12 regions each (one Secure/one Non-Secure) |
| Security Attribute Unit (SAU) | Absent | Absent |
| Implementation Defined Attribution Unit (IDAU) | Absent | Present |
| SysTick timers | One SysTick timer | Two timers (One Secure/One Non-Secure) |
| Vector Table Offset Register | Present (one Vector table) | Present (two Vector tables) |
| Reset all registers | Absent | Absent |
| Multiplier | Fast (one cycle) | Fast (one cycle) |
| Divider | Fast (17 cycles) | Fast (17 cycles) |
| Interrupts | 71(1) | 71(1) |
| Instruction fetch width | 32-bit | 32-bit |
| Single-cycle I/O port | Present | Present |
| Architectural clock gating present | Present | Present |
| Data endianness | Little-endian | Little-endian |
| Halting debug support | Present | Present |
| Wake-up interrupt controller (WIC) | Absent | Absent |
| Number of breakpoint comparators | 4 | 4 |
| Number of watchpoint comparators | 2 | 2 |
| Cross Trigger Interface (CTI) | Absent | Absent |
| Micro Trace Buffer (MTB) | Absent | Absent |
| Embedded Trace Macrocell (ETM) | Absent | Absent |
| JTAGnSW debug protocol | Serial-Wire | Serial-Wire |
| Multi-drop for Serial Wire | Absent | Absent |
Note:
- Refer to the table Interrupt Line Mapping for additional information.
For additional information, refer to the “Arm Cortex-M23 Processor Technical Reference Manual” which is available for download at (www.arm.com).