22.6.3 Power Configuration

Name: PWCFG
Offset: 0x03
Reset: 0x00
Property: PAC Write-Protection

Bit 76543210 
       RAMPSWC[1:0] 
Access R/WR/W 
Reset 00 

Bits 1:0 – RAMPSWC[1:0] SRAM Power Switch Configuration

CAUTION: This configuration takes effect immediately, hence, the user must ensure that no access is performed on a SRAM sub-block which is switched OFF.

When a SRAM sub-block is switched from OFF to ON state, 1 µs delay is required before re-accessing it.

Table 22-8. 512 KB Flash Devices
ValueNameDefinition
0x064 KB64 KB Available
0x148 KB48 KB Available
0x232 KB32 KB Available
0x316 KB16 KB Available
Table 22-9. 256 KB Flash Devices
ValueNameDefinition
0x032 KB32 KB Available
0x132 KB32 KB Available
0x232 KB32 KB Available
0x316 KB16 KB Available
Table 22-10. 128 KB Flash Devices
ValueNameDefinition
0x016 KB16 KB Available
0x112 KB12 KB Available
0x28 KB8 KB Available
0x34 KB4 KB Available