16.11.10 Configuration
| Name: | CFG |
| Offset: | 0x001C |
| Reset: | 0x00000002 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DCCDMALEVEL1 | DCCDMALEVEL0 | LQOS[1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 1 | 0 | |||||
Bit 3 – DCCDMALEVEL1 DMA TriggerLevel 1
| Value | Name | Description |
|---|---|---|
| 0x0 | READ | DCC1 trigger is the image of STATUSB.DCC1D, this signals to the DMA that a data is available for read, this is the correct configuration for a channel that reads DCC1. |
| 0x1 | WRITE | DCC1 trigger is the image of STATUSB.DCC1D inverted, this signals to the DMA that DCC1 is ready for write, this is the correct configuration for a channel that writes DCC1. |
Bit 2 – DCCDMALEVEL0 DMA TriggerLevel 0
| Value | Name | Description |
|---|---|---|
| 0x0 | READ | DCC0 trigger is the image of STATUSB.DCC0D, this signals to the DMA that a data is available for read, this is the correct configuration for a channel that reads DCC0. |
| 0x1 | WRITE | DCC0 trigger is the image of STATUSB.DCC0D inverted, this signals to the DMA that DCC0 is ready for write, this is the correct configuration for a channel that writes DCC0. |
Bits 1:0 – LQOS[1:0] Latency Quality Of Service
Defines the latency quality of service required when accessing the RAM:
0: Background Transfers
1: Bandwidth Sensitive
2: Latency sensitive
3: Latency critical