10.1.6.10 Image Sensor Controller (ISC)

ISC timings are provided in the following conditions:

1.8V domain: VDDIO from 1.7V to 1.9V, maximum external capacitor = 10 pF, DRV = 1, SR = 1
3.3V domain: VDDIO from 3.0V to 3.6V, maximum external capacitor = 10 pF, DRV = 0, SR = 1

Figure 10-34. ISC Timing Diagram

Table 10-36. ISC Timings
Symbol	Parameter	Conditions	Min	Max	Unit
f_{ISC_PCK}	ISC_PCK operating frequency	–	–	100	MHz
ISC1	DATA setup time before ISC_PCK rising edge	–	3.0	–	ns
ISC2	DATA hold time after ISC_PCK rising edge	–	5.0	–	ns
ISC3	VSYNC/HSYNC/FIELD setup time before ISC_PCK rising edge	–	3.0	–	ns
ISC4	VSYNC/HSYNC/FIELD hold time after ISC_PCK rising edge	–	5.0	–	ns