10.1.6.11 LCD Controller (LCDC)

LCD timings are provided in the following conditions:

1.8V domain: VDDIO from 1.7V to 1.9V, maximum external capacitor = 10 pF, DRV = 1, SR = 1
3.3V domain: VDDIO from 3.0V to 3.6V, maximum external capacitor = 10 pF, DRV = 0, SR = 1

Figure 10-35. LCD Timings

Table 10-37. LCD Timings
Symbol	Parameter	Conditions	Min	Max	Unit
f_LCD	Minimum LCD period	–	–	75	MHz
t_VALID	Clock to LCDDAT valid output	–	4.0	–	ns