10.1.6.8 Inter-IC Sound Multi-Channel Controller (I2SMCC)

I2SMCC timings are provided in the following conditions:

1.8V domain: VDDIO from 1.7V to 1.9V, maximum external capacitor = 10 pF, DRV = 1, SR = 1
3.3V domain: VDDIO from 3.0V to 3.6V, maximum external capacitor = 10 pF, DRV = 0, SR = 1

Figure 10-29. I2SMCC Timing Diagram in Host Mode

Figure 10-30. I2SMCC Timing Diagram in Client Mode

Table 10-32. I2SMCC Timings
Symbol	Parameter	Conditions	Min	Max	Unit
Host Mode
f_{I2SMCC_SCK}	I2SMCC_SCK frequency	–	–	25.0	MHz
I2S₀	I2SMCC_DINx setup time before I2SMCC_SCK rises	–	14.0	–	ns
I2S₁	I2SMCC_DINx hold time after I2SMCC_SCK rises	–	2.0	–	ns
I2S₂	I2SMCC_SCK falling to I2SMCC_DOUTx delay	–	-2.0	12.0	ns
I2S₃	I2SMCC_SCK falling to I2SMCC_WS delay	–	-2.0	12.0	ns
Client Mode
f_{I2SMCC_SCK}	I2SMCC_SCK frequency	–	–	25.0	MHz
I2S₄	I2SMCC_DINx setup time before I2SMCC_SCK rises	–	14.0	–	ns
I2S₅	I2SMCC_DINx hold time after I2SMCC_SCK rises	–	2.0	–	ns
I2S₆	I2SMCC_WS setup time before I2SMCC_SCK rises	–	14.0	–	ns
I2S₇	I2SMCC_WS hold time after I2SMCC_SCK rises	–	2.0	–	ns
I2S₈	I2SMCC_SCK falling to I2SMCC_DOUTx delay	–	-2.0	12.0	ns