8.4.6.8.6 Instruction Frame Transmission

If the instruction frame includes the instruction code and/or the option code, the user must configure the fields WRINST, WROPT, RDINST and RDOPT in the Write Instruction Code register (QSPI_WICR) and the Read Instruction Code register (QSPI_RICR). QSPI_WICR configures instruction code and option code for write accesses, and QSPI_RICR configures instruction code and option code for read accesses. For a frame without data (QSPI_IFR.DATAEN=0), QSPI_WICR is used for instruction and option codes.

QSPI_IFR must be configured with the instruction frame to send.

The instruction frame is configured by the following QSPI_IFR bits and fields:

• WIDTH field—configures which data lanes are used to send the instruction code, the address, the option code and to transfer the data.
• INSTEN bit—enables an instruction code.
• ADDREN bit—enables an address after the instruction code.
• OPTEN bit—enables an option code after the address.
• DATAEN bit—enables the transfer of data (READ or PROGRAM instruction).
• OPTL field—configures the option code length. The value written in OPTL must be consistent with the value written in the field WIDTH. For example: OPTL=0 (1-bit option code) is not consistent with WIDTH = 6 (option code sent with QuadSPI protocol, thus the minimum length of the option code is 4 bits).
• ADDRL bit—configures the QSPI address field size.
• TFRTYP field—defines the type of memory access. See the table below.
• CRM bit—enables Continuous Read mode, see Continuous Read Mode.
• DDREN bit—configures the Double Data Rate mode; the instruction code is still transmitted in Single Data Rate mode. The instruction code can be transmitted in DDR mode by writing a 1 to QSPI_IFR.DDRCMDEN.
• NBDUM field—configures the number of dummy cycles when reading data from the serial Flash memory. Between the address/option and the data, with some instructions, dummy cycles are required by the serial Flash memory.
• END bit—defines the endianness of the targeted memory.
• SMRM bit—when TFRTYP=0, defines if the instruction frame transmission is triggered by register accesses or QSPI memory space accesses.
• APBTFRTYP bit—defines the peripheral bus register transfer to memory type (read or write) when QSPI_IFR.TFRTYP is written to 0.
• DQSEN bit—defines if the targeted memory supplies a DQS signal.
• DDRCMDEN bit—defines if the instruction code must be sent in DDR mode when QSPI_IFR.DDREN bit is written to 1.
• HFWBEN field—enables the HyperFlash Write Buffer command support. In this mode, a new command is generated for each write access. See HyperFlash Mode.
• PROTTYP bit—defines the QSPI protocol type.

See Instruction Frame register.

Depending on TFRTYP and SMRM memory accesses, the applicable methods are as follows.