8.4.6.8.14 HyperFlash Mode

The QSPI supports HyperFlash memories. To enable HyperFlash mode, set QSPI_IFR.PROTTYP to 3.

See examples 13 and 14 in Instruction Frame Transmission Examples.

HyperFlash memories use Octal DDR communication. Recommendations provided in Octal DDR Mode must be followed.

HyperFlash memories define a “command/address” field where the address of the transfer is included and merged in the command. For this reason, in this mode QSPI_IFR.ADDREN must be set to 0 and QSPI_IFR.INSTEN must be set to 1.

The HyperFlash “command/address” field merges the transfer address and the transfer characteristics (such as read/write, memory/register space, burst type, etc.) so that there is no specific opcode per transfer type. As a consequence, QSPI_WICR and QSPI_RICR are not used in this mode. See the following figure.

Once HyperFlash mode is enabled, the procedure to access the memory is the same as for classic QSPI memories. See Instruction Frame Transmission (see Figure 8-167, Figure 8-168, Figure 8-171, Figure 8-173, Figure 8-175).

For the HyperFlash Write Buffer procedure, QSPI_IFR.HFWBEN must be set. When this bit is set, a new command is issued for each halfword written. In this mode, halfword accesses are mandatory. See Figure 8-176 and Figure 8-177.

1. In HyperFlash mode, some bits of the HyperFlash command are set automatically. For instance, the “Burst Type” bit of the HyperFlash command (bit 45) is always set to 1 (linear burst).
2. The HyperFlash standard latency definition counts the latency starting from the fourth byte of the instruction, whereas the QSPI IP counts the dummy cycles starting from the end of the instruction field. Therefore, the value to set in QSPI_IFR.NBDUM is the HyperFlash latency value minus 1.