8.4.6.8.11 Twin-Quad Mode
The Twin-Quad mode is activated by writing a 1 to QSPI_IFR.PROTTYP (Twin-Quad protocol). In this mode, the QSPI communicates with two Quad SPI memories as a single octal memory.
See examples 11 and 12 in Instruction Frame Transmission Examples.
In this mode, only the DUAL_CMD, OCT_OUTPUT, OCT_IO and OCT_CMD configurations are supported by QSPI_IFR.WIDTH.
- DUAL_CMD: addresses both dies included in the Twin-Quad memory in single bit SPI for the Instruction, Address and Data phases (1-1-1).
- OCT_OUTPUT: addresses both dies included in the Twin-Quad memory in single bit SPI for the Instruction and Address phases, then in Quad SPI for the Data phase (1-1-4).
- OCT_IO: addresses both dies included in the Twin-Quad memory in single bit SPI for the Instruction phase, then in Quad SPI for the Address and Data phases (1-4-4).
- OCT_CMD: addresses both dies included in the Twin-Quad memory in Quad SPI for the Instruction, Address and Data phases (4-4-4).
When QSPI_IFR.TFRTYP is written to 1, programming is the same as in the standard Quad SPI protocol.
When QSPI_IFR.TFRTYP is written to 0, programming differs due to the fact that each Quad SPI die has its own internal registers.
If QSPI_MR.SMRM is written to 0 (see Instruction Frame Transmission), a halfword read/write transfer must be issued instead of a byte transfer (one byte for each register of each die) to the Twin-Quad memory to write/read the registers of both dies.
- For read transfers, the halfword read is as follows: {reg_byte[3:0],
reg_byte[3:0], reg_byte[7:4], reg_byte[7:4]}.
- Example: if data 0xA7 is to be read in both registers of both dies, the halfword read will be 0x77AA.
- For write transfers, the halfword must be sent as follows:
{reg_byte[3:0], reg_byte[3:0], reg_byte[7:4], reg_byte[7:4]}.
- Example: if data 0xB5 is to be written in both registers of both dies, the halfword to write is 0x55BB.
If QSPI_MR.SMRM is written to 1 (see Instruction Frame Transmission), a two-byte read/write transfer must be issued instead of a one-byte transfer (one byte for each register of each die) to the Twin-Quad memory to write/read the registers of both dies.
- For read transfers, the first byte read is {reg_byte[3:0],
reg_byte[3:0]}. The second byte read is {reg_byte[7:4], reg_byte[7:4]}.
- Example: if data 0xA7 is read in both registers of both dies, the first byte read is 0xAA and the second byte read is 0x77.
- For write transfers, the first byte sent must be {reg_byte[3:0],
reg_byte[3:0]}. The second byte sent must be {reg_byte[7:4], reg_byte[7:4]}.
- Example: if data 0xB5 is to be written in both registers of both dies, the first byte to write is 0xBB and the second byte to write is 0x55.
If QSPI_IFR.WIDTH is configured to OCT_CMD, and DDREN is written to 1, then a halfword must be read/written instead of a byte for each QSPI_RDR or QSPI_TDR access.
In this configuration, the halfword to write in QSPI_TDR in case of a write transfer is {reg_byte[7:4], reg_byte[7:4], reg_byte[3:0], reg_byte[3:0]}.
For example, if data 0xB5 is to be written in both registers of both dies, the halfword to write in QSPI_TDR is 0xBB55.
In this configuration, the halfword read in QSPI_RDR in case of a read transfer is {reg_byte[7:4], reg_byte[7:4], reg_byte[3:0], reg_byte[3:0]}.
For example, if data 0xA7 is to be read in both registers of both dies, the halfword read in QSPI_RDR is 0xAA77.