1.12 Peripheral Identifiers

Table 1-6. Peripheral Identifiers
Instance IDInstance NameInternal InterruptExternal
 InterruptWired-ORPMC 
Clock ControlMain System Bus ClockGeneric ClockfGCLK (Max)PLLADIV2CLKUPLLCLKAUDIOPLLInstance Description
0AICFIQMCKAdvanced Interrupt Controller
1SYSCXSYSC, PMC, WDT, PIT, RSTC, RTT, RTCMCKLogical-OR Interrupt of SYSC, PMC, WDT, PIT, RSTC, RTT, RTC
2PIOAXXMCKParallel I/O Controller A
3PIOBXPB18XMCKParallel I/O Controller B
4PIOCXXMCKParallel I/O Controller C
5FLEXCOM0XXMCKXfMCK/3XFLEXCOM 0
6FLEXCOM1XXMCKXfMCK/3XFLEXCOM 1
7FLEXCOM2XXMCKXfMCK/3XFLEXCOM 2
8FLEXCOM3XXMCKXfMCK/3XFLEXCOM 3
9FLEXCOM6XXMCKXfMCK/3XFLEXCOM 6
10FLEXCOM7XXMCKXfMCK/3XFLEXCOM 7
11FLEXCOM8XXMCKXfMCK/3XFLEXCOM 8
12SDMMC0XXMCKX105XXSecure Data Memory Card Controller 0
13FLEXCOM4XXMCKXfMCK/3XFLEXCOM 4
14FLEXCOM5XXMCKXfMCK/3XFLEXCOM 5
15FLEXCOM9XXMCKXfMCK/3XFLEXCOM 9
16FLEXCOM10XXMCKXfMCK/3XFLEXCOM 10
17TC0XXMCKXfMCK/3XXTimer Counters 0,1,2
18PWMXXMCKPulse Width Modulation Controller
19ADCXXMCKXfMCK/3XXADC Controller
20XDMACXXMCKExtended DMA Controller
21MATRIXXMCKMatrix
22UHPHSXXMCKUSB Host High Speed
23UDPHSXXMCKUSB Device High Speed
24GMACXXMCKX50XXGigabit Ethernet MAC
25LCDCXXMCKX75XXLCD Controller
26SDMMC1XXMCKX105XXSecure Data Memory Card Controller 1
27ReservedMCK
28SSCXXMCKSynchronous Serial Controller
29MCAN0XXMCKX80XXCAN Controller 0
30MCAN1XXMCKX80XXCAN Controller 1
31AICIRQMCKAdvanced Interrupt Controller
32FLEXCOM11XXMCKXfMCK/3XFLEXCOM 11
33FLEXCOM12XXMCKXfMCK/3XFLEXCOM 12
34I2SMCCXXMCKX100XXI2S Multi Channel Controller
35QSPIXXMCK(1)X200XXQuad I/O SPI Controller
36GFX2DXXMCK2D Graphics Controller
37PIT64B0XXMCKXfMCK/3X64-bit Timer
38TRNGXXMCKTrue Random Number Generator
39AESXXMCKAdvanced Encryption Standard
40TDESXXMCKTriple Data Encryption Standard
41SHAXXMCKSecure Hash Algorithm
42CLASSDXXMCKX100XXCLASS D Controller
43ISIXXMCKImage Sensor Interface
44PIODXXMCKParallel I/O Controller D
45TC1XXMCKXfMCK/3XXTimer Counter 3, 4, 5
46OTPCXMCKOTP Controller
47DBGUXXMCKXfMCK/3XDebug Unit
48PMECCXPMECC, PMERRLOCMCKLogical-OR Interrupt of PMECC and PMERRLOC
49MPDDRCXMPDDRC, SMCXMCKLogical-OR Interrupt of MPDDRC and HSMC
50UTMIMCKUTMI Controller
51Reserved
52CSI2DCXXMCKCSI to Demultiplexer Controller
53CSIXXMCKCamera Serial Interface between ISC and MIPI D-PHY
54DSIXXMCKDisplay Serial Interface between LCDC and MIPI D-PHY
55MIPIPHYX27XMIPI D-PHY interface
56LVDSCXXDisplay Serial Interface between LCDC and LVDS Interface
57LVDSPHYLVDS Physical Interface
58PIT64B1XXMCKXfMCK/3XX64-bit Timer 1
59PUFXMCKPUF controller
60GMACQ1GMAC Queue 1 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 1
61GMACQ2GMAC Queue 2 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 2
62GMACQ3GMAC Queue 3 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 3
63GMACQ4GMAC Queue 4 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 4
64GMACQ5GMAC Queue 5 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 5
65GMACEMACExpress MAC
66GMACMMSLMAC Merge Sublayer
67Reserved
68MCAN0INT1MCAN0 Interrupt 1
69MCAN1INT1MCAN1 Interrupt 1
Note:
  1. This QSPI GCLK is a 2x clock. It must be set to 200 MHz to reach 100 MHz on the data.