1.7 Signal Description
| Signal Name | Function | Type | Comments | Active Level |
|---|---|---|---|---|
| Clocks, Oscillators and PLLs | ||||
| XIN | Main Crystal Oscillator Input | Input | – | – |
| XOUT | Main Crystal Oscillator Output | Output | – | – |
| XIN32 | 32.768 kHz Crystal Oscillator Input | Input | – | – |
| XOUT32 | 32.768 kHz Crystal Oscillator Output | Output | – | – |
| RTUNE | USB External Tune Resistor | Analog | – | – |
| PCK[1:0] | Programmable Clock Output | Output | – | – |
| AUDIOCLK | Audio Programmable Clock Output | Output | – | – |
| Shutdown, Wake-Up Logic | ||||
| SHDN | Shutdown Control | Output | – | – |
| WKUP0 | Wake-Up Input | Input | – | – |
| ICE and JTAG | ||||
| TCK | Test Clock | Input | – | – |
| TDI | Test Data In | Input | – | – |
| TDO | Test Data Out | Output | – | – |
| TMS | Test Mode Select | Input | – | – |
| JTAGSEL | JTAG Selection | Input | – | – |
| RTCK | Return Test Clock | Output | – | – |
| Reset/Test | ||||
| NRST | External Reset Input | Input | – | Low |
| NRST_OUT | Reset Controller Output | Output | – | Low |
| TST | Test Mode Select | Input | – | – |
| NTRST | Test Reset Signal | Input | – | – |
| Debug Unit - DBGU | ||||
| DRXD | Debug Receive Data | Input | – | – |
| DTXD | Debug Transmit Data | Output | – | – |
| Advanced Interrupt Controller - AIC | ||||
| IRQ | External Interrupt Input | Input | – | – |
| FIQ | Fast Interrupt Input | Input | – | – |
| PIO Controller - PIOA - PIOB - PIOC - PIOD | ||||
| PA[31:0] | Parallel IO Controller A | I/O | – | – |
| PB[26:0] | Parallel IO Controller B | I/O | – | – |
| PC[31:0] | Parallel IO Controller C | I/O | – | – |
| PD[14:0] | Parallel IO Controller D | I/O | – | – |
| External Bus Interface - EBI | ||||
| A[22:0] | Address Bus | Output | – | – |
| NWAIT/NANDRDY | External Wait Signal/NAND Flash R/B Signal | Input | – | Low |
| Static Memory Controller - SMC | ||||
| NCS[2:0] | Chip Select Lines | Output | – | Low |
| NWR[1:0] | Write Signal | Output | – | Low |
| NRD | Read Signal | Output | – | Low |
| NWE | Write Enable | Output | – | Low |
| NBS[1:0] | Byte Mask Signal | Output | – | Low |
| NAND Flash Controller | ||||
| NANDDAT[7:0] | NAND Flash I/O | I/O | – | – |
| NANDCS | NAND Flash Chip Select | Output | – | Low |
| NANDOE | NAND Flash Output Enable | Output | – | Low |
| NANDWE | NAND Flash Write Enable | Output | – | Low |
| NANDALE | NAND Address Latch Enable | Output | – | Low |
| NANDCLE | NAND Command Latch Enable | Output | – | Low |
| DDR2/DDR3(L) Controller | ||||
| SDCK | DRAM Clock | Output | – | – |
| SDCKN | DRAM Clock Bar | Output | – | – |
| SDCKE | DRAM Clock Enable | Output | – | High |
| DDRCS | DRAM Chip Select | Output | – | Low |
| BA[2:0] | Bank Select | Output | – | Low |
| SDWE | DRAM Write Enable | Output | – | Low |
| DDR_VREF | I/O Reference Voltage | I/O | – | – |
| DDR_CAL | Calibration Input | I/O | – | – |
| RAS - CAS | Row and Column Signal | Output | – | Low |
| A[22:0] | Address Bus | Output | – | – |
| SDA10 | SDRAM Address 10 Line | Output | – | – |
| D[15:0] | Data Bus | I/O | – | – |
| DQS[1:0] | Positive Data Strobe | I/O | – | – |
| DQSN[1:0] | Negative Data Strobe (DDR2/3(L)-SDRAM only) | I/O | – | – |
| DQM[1:0] | Write Data Mask | Output | – | – |
| RESETN | DDR3-SDRAM Reset | Output | – | – |
| Secure Data Memory Card - SDMMCx [1:0] | ||||
| SDMMCx_CMD | SD Card/e.MMC Command Line | I/O | – | – |
| SDMMCx_CK | SD Card/e.MMC Clock Signal | Output | – | – |
| SDMMCx_DAT[3:0] | SD Card/e.MMC Data Lines | I/O | – | – |
| Flexible Serial Communication Controller - FLEXCOMx [12:0] | ||||
| FLEXCOMx_IO0 | Transmit Data (TXD/MOSI/TWD) | I/O | – | – |
| FLEXCOMx_IO1 | Receive Data (RXD/MISO/TWCK) | I/O | – | – |
| FLEXCOMx_IO2 | Serial Clock (SCK/SPCK) | I/O | – | – |
| FLEXCOMx_IO3 | Clear To Send/Peripheral Chip Select | I/O | – | – |
| FLEXCOMx_IO4 | Request To Send/Peripheral Chip Select | Output | – | – |
| FLEXCOMx_IO5 | Peripheral Chip Select | Output | – | – |
| FLEXCOMx_IO6 | Peripheral Chip Select | Output | – | – |
| FLEXCOMx_IO7 | LON Collision | Input | – | – |
| Synchronous Serial Controller - SSC | ||||
| TD | Transmit Data | Output | – | – |
| RD | Receive Data | Input | – | – |
| TK | Transmit Clock | I/O | – | – |
| RK | Receive Clock | I/O | – | – |
| TF | Transmit Frame Synchronization | I/O | – | – |
| RF | Receive Frame Synchronization | I/O | – | – |
| Timer/Counter - TCx [5:0] | ||||
| TCLK[2:0] | External Clock Input | Input | – | – |
| TIOA[2:0] | I/O Line A | I/O | – | – |
| TIOB[2:0] | I/O Line B | I/O | – | – |
| Pulse Width Modulation Controller - PWMC | ||||
| PWM[3:0] | Pulse Width Modulation Output | Output | – | – |
| USB Host High Speed Port - UHPHS | ||||
| HHSDMA | USB Host Port A High Speed Data - | Analog | – | – |
| HHSDPA | USB Host Port A High Speed Data + | Analog | – | – |
| HHSDMB | USB Host Port B High Speed Data - | Analog | – | – |
| HHSDPB | USB Host Port B High Speed Data + | Analog | RTUNE | – |
| HHSDMC | USB Host Port C High Speed Data - | Analog | – | – |
| HHSDPC | USB Host Port C High Speed Data + | Analog | – | – |
| USB Device High Speed Port - UDPHS | ||||
| DHSDM | USB Device High Speed Data - | Analog | – | – |
| DHSDP | USB Device High Speed Data + | Analog | – | – |
| Gigabit Ethernet 10/100/1000 with IEEE-1588 and TSN (RGMII/RMII only) - GMAC | ||||
| GTXCK/GREFCK | Transmit Clock or Reference Clock | I/O | – | – |
| G125CK | 125 MHz Reference Clock | Input | – | – |
| GRXCK | Receive Clock | Input | – | – |
| GTXEN/GTXCTL | Transmit Enable or Transmit Control | Output | – | – |
| GTX[3:0] | Transmit Data | Output | – | – |
| GCRSDV/GRXCTL | Receive Data Valid or Receive Control | Input | – | – |
| GRX[3:0] | Receive Data | Input | – | – |
| GRXER | Receive Error | Input | – | – |
| GMDC | Management Data Clock | Output | – | – |
| GMDIO | Management Data Input/Output | I/O | – | – |
| GTSUCOMP | TSU Timer Comparison Valid | Output | – | – |
| Analog-to-Digital Converter - ADC | ||||
| AD[7:0] | 8 Analog Inputs | Input | – | – |
| ADTRG | ADC Trigger | Input | – | – |
| ADVREFN | ADC Negative Reference Voltage | Analog Input | – | – |
| ADVREFP | ADC Positive Reference Voltage | Analog Input | – | – |
| CAN Controller - CANx [1:0] | ||||
| CANRXx | CAN Receive | Input | – | – |
| CANTXx | CAN Transmit | Output | – | – |
| Class D Controller - CLASSD | ||||
| CLASSD_L0 | Class D Controller Left Output 0 | Output | – | – |
| CLASSD_L1 | Class D Controller Left Output 1 | Output | – | – |
| CLASSD_L2 | Class D Controller Left Output 2 | Output | – | – |
| CLASSD_L3 | Class D Controller Left Output 3 | Output | – | – |
| CLASSD_R0 | Class D Controller Right Output 0 | Output | – | – |
| CLASSD_R1 | Class D Controller Right Output 1 | Output | – | – |
| CLASSD_R2 | Class D Controller Right Output 2 | Output | – | – |
| CLASSD_R3 | Class D Controller Right Output 3 | Output | – | – |
| Quad/Octal I/O SPI - QSPI | ||||
| QSCK | Quad IO SPI Serial Clock | Output | – | – |
| QCS | Quad IO SPI Chip Select | Output | – | – |
| QIO[7:0] | IO SPI I/O 0 to 7 | I/O | – | – |
| QDQS | Octal IO Data Strobe | I/O | – | – |
| QINT | Interrupt | Input | – | – |
| Inter IC Sound Multi Channel Controller - I2SMCC | ||||
| I2SMCC_MCK | Main System Bus Clock | Output | – | – |
| I2SMCC_CK | Serial Clock | I/O | – | – |
| I2SMCC_WS | I2S Word Select | I/O | – | – |
| I2SMCC_DIN | Serial Data Input | Input | – | – |
| I2SMCC_DOUT | Serial Data Output | Output | – | – |
| MIPI D-PHY | ||||
|
MIPI_DP[3:0] MIPI_DN[3:0] | MIPI D-PHY Differential Output Data Lane [3:0] | I/O | – | – |
|
MIPI_CLKP MIPI_CLKN | MIPI D-PHY Differential Output Clock Lane | I/O | – | – |
| MIPI_REXT | Calibration Reference Resistor (4.02 KΩ E96) | I/O | – | – |
| Low Voltage Differential Signaling Controller (LVDS) | ||||
|
LVDS_A[3:0]P LVDS_A[3:0]M | Differential LVDS Data Line Transceiver Output [3:0] | Output | – | – |
|
LVDS_CLK1M LVDS_CLK1P | Differential LVDS Clock Line Transceiver Output | Output | – | – |
| Image Sensor Controller (ISC) | ||||
| ISC_MCK | Main System Bus Clock to Sensor | Output | – | – |
| ISC_PCK | Pixel Clock from Sensor | Input | – | – |
| ISC_D[11:0] | Data | Input | – | – |
| ISC_HSYNC | Horizontal Synchronization | Input | – | – |
| ISC_VSYNC | Vertical Synchronization | Input | – | – |
| ISC_FIELD | Field to Interface Video Streams | Input | – | – |
| LCD Controller (LCDC) | ||||
| LCDC_DAT[23:0] | Data Bus | Output | – | – |
| LCDC_PCK | Pixel Clock | Output | – | – |
| LCDC_HSYNC | Horizontal Synchronization | Output | – | – |
| LCDC_VSYNC | Vertical Synchronization | Output | – | – |
| LCDC_DEN | Data Enable | Output | – | – |
| LCDC_DISP | Display On/Off | Output | – | – |
| LCDC_PWM | PWM for Contrast Control | Output | – | – |