The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
Name:
TC_IMRx
Offset:
0x2C + x*0x40 [x=0..2]
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
SECE
Access
R
Reset
0
Bit
7
6
5
4
3
2
1
0
ETRGS
LDRBS
LDRAS
CPCS
CPBS
CPAS
LOVRS
COVFS
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit 10 – SECE Security and/or Safety Event Interrupt Mask
Bit 7 – ETRGS External Trigger
Bit 6 – LDRBS RB Loading
Bit 5 – LDRAS RA Loading
Bit 4 – CPCS RC Compare
Bit 3 – CPBS RB Compare
Bit 2 – CPAS RA Compare
Bit 1 – LOVRS Load Overrun
Bit 0 – COVFS Counter Overflow
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
