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Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI® or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
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Product Pages
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5
Image Subsystem
5.1
Overview
5.1.3
Product Dependencies
5.1.3.3
Reset
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
5
Image Subsystem
5.1
Overview
5.1.1
Block Diagram
5.1.2
Components
5.1.3
Product Dependencies
5.1.3.1
Clocks
5.1.3.2
Interrupts
5.1.3.3
Reset
5.1.3.4
I/Os
5.1.3.5
Power Saving
5.1.4
LVDS I/O Configuration
5.1.5
Special Functions in SFR
5.2
LCD Controller (LCDC)
5.3
Low Voltage Differential Signaling Controller (LVDSC)
5.4
2D Graphics Engine (GFX2D)
5.5
Display Serial Interface (DSI)
5.6
Camera Serial Interface (CSI)
5.7
CSI-2 Demultiplexer Controller (CSI2DC)
5.8
Image Sensor Controller (ISC)
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
5.1.3.3 Reset
Image peripherals are connected to the processor and peripherals reset line.
