The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
Name:
DBGU_IMR
Offset:
0x0010
Reset:
0x0000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
COMMRX
COMMTX
Access
R
R
Reset
0
0
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
TXEMPTY
TIMEOUT
Access
R
R
Reset
0
0
Bit
7
6
5
4
3
2
1
0
PARE
FRAME
OVRE
TXRDY
RXRDY
Access
R
R
R
R
R
Reset
0
0
0
0
0
Bit 31 – COMMRX Mask COMMRX (from Arm)
Interrupt
Bit 30 – COMMTX Mask COMMTX (from Arm)
Interrupt
Bit 9 – TXEMPTY Mask TXEMPTY Interrupt
Bit 8 – TIMEOUT Mask Timeout Interrupt
Bit 7 – PARE Mask Parity Error Interrupt
Bit 6 – FRAME Mask Framing Error Interrupt
Bit 5 – OVRE Mask Overrun Error Interrupt
Bit 1 – TXRDY Disable TXRDY Interrupt
Bit 0 – RXRDY Mask RXRDY Interrupt
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