8.4.2 Embedded Characteristics

  • Host SPI Interface
    • Octal/Quad/Dual/Single/Twin-Quad communication support
    • Single Data Rate (SDR) and Dual Data Rate (DDR) support
    • Flash/NANDmemory support (supports various vendors and modes)
    • Supports “Execute in Place” (XiP)—code execution by the system directly from a serial memory
  • Legacy SPI Mode
    • Interface to serial peripherals such as ADCs and sensors
    • 8-bit/16-bit programmable data length
  • Serial Memory Mode
    • Versatile instruction and timing registers for compatibility with all serial Flash memories and SPI devices
    • Up to 32-bit address mode to support serial Flash memories larger than 128 Mbits
    • “On-the-fly” zero latency scrambling/unscrambling
  • Functional Safety Monitors and Reports
    • Abnormal functional behavior reports (access to undefined device address, access to locked registers, abnormal DMA requests, etc.)
    • Register write protection
  • Connection to DMA Channel Capabilities for DMA Chip-Wide Integration
    • One channel for the receiver, one channel for the transmitter
  • Supported standards are:
    • JESD251 (xSPI)
    • JESD251-1 (x4 Quad I/O with Data Strobe)
    • JESD216D (SFDP)