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Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI® or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
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8
Connectivity Subsystem
8.4
Quad Serial Peripheral Interface (QSPI)
8.4.6
Functional Description
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
5
Image Subsystem
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
8.1
Overview
8.2
Ethernet MAC (GMAC)
8.3
Flexible Serial Communication Controller (FLEXCOM)
8.4
Quad Serial Peripheral Interface (QSPI)
8.4.1
Description
8.4.2
Embedded Characteristics
8.4.3
Block Diagram
8.4.4
Signal Description
8.4.5
Product Dependencies
8.4.6
Functional Description
8.4.6.1
Register Synchronization
8.4.6.2
Updating the QSPI Configuration
8.4.6.3
Serial Clock Phase and Polarity
8.4.6.4
Transfer Delays
8.4.6.5
DQS Delay
8.4.6.6
Refresh Sequence
8.4.6.7
QSPI SPI Mode
8.4.6.8
QSPI Serial Memory Mode
8.4.6.9
Scrambling/Unscrambling Function
8.4.6.10
Register Write Protection
8.4.6.11
Peripheral Bus Access Errors
8.4.7
Register Summary
8.5
Secure Digital MultiMedia Card Controller (SDMMC)
8.6
Controller Area Network (MCAN)
8.7
Timer Counter (TC)
8.8
Pulse Width Modulation Controller (PWM)
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
8.4.6 Functional Description
