3.2.5.1 Hardware Interface

The following table details the connections to be applied between the EBI pins and the external devices for each memory controller.

Table 3-3. EBI Pins and External Static Device Connections
Signals: EBI_	Pins of the Interfaced Device
Signals: EBI_	8-bit  Static Device	2 x 8-bit  Static Devices	16-bit  Static Device
Controller	SMC
D[7:0]	D[7:0]	D[7:0]	D[7:0]
D[15:8]	–	D[15:8]	D[15:8]
A0/NBS0⁽¹⁾	A0	–	NLB
A1⁽¹⁾	A1	A0	A0
A[22:2]⁽¹⁾	A[20:2]	A[19:1]	A[19:1]
NCS0⁽¹⁾	CS	CS	CS
NCS1/DDRCS	CS	CS	CS
NCS2/NANDCS⁽¹⁾	CS	CS	CS
NRD⁽¹⁾	OE	OE	OE
NWR0/NWE⁽¹⁾	WE	WE⁽²⁾	WE
NWR1/NBS1⁽¹⁾	–	WE⁽²⁾	NUB

Note:

A0/NBS0, A1, A12, A19 and A20, NCS0, NCS2/NANDCS, NRD, NWR0/NWE, NWR1/NBS1 are multiplexed on PD[13:4].
NWR1 enables upper byte writes. NWR0 enables lower byte writes.

Table 3-4. EBI Pins and External Device Connections
Signals: EBI_	Power supply	Pins of the Interfaced Device
Signals: EBI_		DDR3(L)/DDR2	NAND Flash
Controller		MPDDRC	NFC
D[7:0]	VDDIOM	D[7:0]	NFD[7:0]⁽¹⁾
D[15:8]	VDDIOM	D[15:8]	–
NANDDAT[7:0]	VDDNF	–	NFD[7:0]⁽¹⁾
A0/NBS0	VDDIOM	–	–
A1	VDDNF	–	–
DQM[1:0]	VDDIOM	DQM[1:0]	–
DQS[1:0], DQSN[1:0]	VDDIOM	DQS[1:0], DQSN[1:0]	–
A[10:2]	VDDIOM	A[8:0]	–
A11	VDDIOM	A9	–
SDA10	VDDIOM	A10	–
A12	VDDNF	–	–
A[14:13]	VDDIOM	A[12:11]	–
A15	VDDIOM	A13	–
A16/BA0	VDDIOM	BA0	–
A17/BA1	VDDIOM	BA1	–
A18/BA2	VDDIOM	BA2	–
A19	VDDNF	–	–
A20	VDDNF	–	–
A21/NANDALE	VDDNF	–	ALE
A22/NANDCLE	VDDNF	–	CLE
NCS0	VDDNF	–	–
NCS1/SDCS	VDDIOM	DDRCS	–
NCS2/NANDCS	VDDNF	–	CE
NANDOE	VDDNF	–	OE
NANDWE	VDDNF	–	WE
NRD	VDDNF	–	–
NWR0/NWE	VDDNF	–	–
NWR1/NBS1	VDDNF	–	–
SDCK	VDDIOM	CK	–
SDCK#	VDDIOM	CK#	–
SDCKE	VDDIOM	CKE	–
RAS	VDDIOM	RAS	–
CAS	VDDIOM	CAS	–
SDWE	VDDIOM	WE	–
NWAIT/NANDRDY	VDDNF	–	NANDRDY

Note:

The NFD0_ON_D16 switch is used to select NAND Flash path on D[7:0] or NANDDAT[7:0] depending on memory power supplies. This switch is located in the SFR_CCFG_EBICSA register in the Special Function Register.