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Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI® or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI® or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
Product Pages
SAM9X70 SAM9X72 SAM9X75
  1. Home
  2. 7 Security and Cryptography Subsystem
  3. 7.6 Physical Unclonable Functions (PUF)
  4. 7.6.5 Functional Description
  5. 7.6.5.7 PUF Operation Restrictions

  • Introduction
  • Reference Document
  • 1 Overview
  • 2 CPU and Interconnect
  • 3 Memories
  • 4 System Controller
  • 5 Image Subsystem
  • 6 Audio Subsystem
  • 7 Security and Cryptography Subsystem
    • 7.1 Overview
    • 7.2 Advanced Encryption Standard (AES)
    • 7.3 Secure Hash Algorithm (SHA)
    • 7.4 Triple Data Encryption Standard (TDES)
    • 7.5 Random Number Generator (TRNG)
    • 7.6 Physical Unclonable Functions (PUF)
      • 7.6.1 Description
      • 7.6.2 Embedded Characteristics
      • 7.6.3 Block Diagram
      • 7.6.4 Product Dependencies
      • 7.6.5 Functional Description
        • 7.6.5.1 PUF Introduction
        • 7.6.5.2 PUF Operations
        • 7.6.5.3 Security Strength Versus Key Length
        • 7.6.5.4 PUF Controller States
        • 7.6.5.5 PUF Controller Operations
        • 7.6.5.6 PUF Data Formats
        • 7.6.5.7 PUF Operation Restrictions
        • 7.6.5.8 PUF Error Handling
        • 7.6.5.9 PUF Diagnostics
        • 7.6.5.10 PUF Built-in Tests
        • 7.6.5.11 PUF Deterministic Random Number Generator (DRNG)
      • 7.6.6 Register Summary
  • 8 Connectivity Subsystem
  • 9 USB Subsystem
  • 10 Electrical and Mechanical Characteristics
  • 11 Revision History
  • Microchip Information

7.6.5.7 PUF Operation Restrictions

The PUF Hardware Settings Register provides information on current restrictions applying to operations.

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