Values in this register
are static and not managed by the PUF.
The following configuration
values are valid for all listed bit names of this register:
0:
The corresponding operation is allowed.
1: The corresponding
operation is disabled.
Name:
PUF_HW_SETTINGS
Offset:
0x0F0
Reset:
–
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
TESTPUF
TESTMEM
MEMTEST
EXTSVIADIR
LABTESTSEL
LABTEST
Access
R
R
R
R
R
R
Reset
–
–
–
–
–
–
Bit
23
22
21
20
19
18
17
16
RESEED
Access
R
Reset
–
Bit
15
14
13
12
11
10
9
8
GENRAND
WRAP
WGENRAND
Access
R
R
R
Reset
–
–
–
Bit
7
6
5
4
3
2
1
0
UNWRAP
GETKEY
STOP
RECO
START
ENROLL
Access
R
R
R
R
R
R
Reset
–
–
–
–
–
–
Bit 31 – TESTPUF Test PUF Operation
Bit 30 – TESTMEM Test Memory Operation
Bit 29 – MEMTEST Memory Tests Included in Initialization
Bit 27 – EXTSVIADIR External Entropy Required via PUF_DIR During Reseed Operation
Bit 25 – LABTESTSEL Selection of Lab Test Mode, when LABTEST=0
Bit 24 – LABTEST Initialization to Lab Test Mode
Bit 16 – RESEED Reseed Operation
Bit 15 – GENRAND Generate Random Operation
Bit 9 – WRAP Wrap Operation
Bit 8 – WGENRAND Wrap Generated Random Operation
Bit 7 – UNWRAP Unwrap Operation
Bit 6 – GETKEY Get Key Operation
Bit 5 – STOP Stop Operation
Bit 3 – RECO Reconstruct Operation
Bit 2 – START Start Operation
Bit 1 – ENROLL Enroll Operation
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
