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Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI® or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
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Product Pages
SAM9X70
SAM9X72
SAM9X75
Home
2
CPU and Interconnect
2.5
Boot Strategies
2.5.1
Standard Boot Strategy
2.5.1.5
SAM-BA Monitor
2.5.1.5.3
USB Device Interface
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
2.1
Arm926EJ-S Processor
2.2
Debug and Test
2.3
Bus Matrix (MATRIX)
2.4
DMA Controller (XDMAC)
2.5
Boot Strategies
2.5.1
Standard Boot Strategy
2.5.1.1
Description
2.5.1.2
Flow Diagram
2.5.1.3
Chip Setup
2.5.1.4
Boot Configuration
2.5.1.5
SAM-BA Monitor
2.5.1.5.1
Command List
2.5.1.5.2
ROM Code Console Interface
2.5.1.5.3
USB Device Interface
2.5.1.5.3.1
Supported External Crystal or External Clocks
2.5.1.5.3.2
USB Class
2.5.1.5.3.3
Enumeration Process
2.5.1.5.3.4
Communication Endpoints
2.5.2
Secure Boot Strategy
2.5.3
Software Considerations
2.5.4
Hardware Considerations
3
Memories
4
System Controller
5
Image Subsystem
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
2.5.1.5.3 USB Device Interface
