35.6.2.6 Waveform Output Generation Operations

The compare channels can be used for waveform generation on output port pins. To make the waveform available on the connected pin, the following requirements must be fulfilled:
  1. Choose a waveform generation mode in the Waveform Generation Operation bit in Waveform register (WAVE.WAVEGEN).
  2. Optionally invert the waveform output WO[x] by writing the corresponding Waveform Output x Inversion bit in the Driver Control register (DRVCTRL.INVENx).
  3. Configure the pins with the I/O Pin Controller. Refer to PORT - I/O Pin Controller for details.

The counter value is continuously compared with each CCx value. On a comparison match, the Match or Capture Channel x bit in the Interrupt Flag Status and Clear register (INTFLAG.MCx) will be set on the next zero-to-one transition of CLK_TCC_COUNT (see Normal Frequency Operation). An interrupt and/or event can be generated on the same condition if Match/Capture occurs, i.e. INTENSET.MCx and/or EVCTRL.MCEOx is '1'. Both interrupt and event can be generated simultaneously. The same condition generates a DMA request.

There are seven waveform configurations for the Waveform Generation Operation bit group in the Waveform register (WAVE.WAVEGEN). This will influence how the waveform is generated and impose restrictions on the top value. The configurations are:
  • Normal Frequency (NFRQ)
  • Match Frequency (MFRQ)
  • Normal Pulse-Width Modulation (NPWM)
  • Dual-slope, interrupt/event at TOP (DSTOP)
  • Dual-slope, interrupt/event at ZERO (DSBOTTOM)
  • Dual-slope, interrupt/event at Top and ZERO (DSBOTH)
  • Dual-slope, critical interrupt/event at ZERO (DSCRITICAL)

When using MFRQ configuration, the TOP value is defined by the CC0 register value. For the other waveform operations, the TOP value is defined by the Period (PER) register value.

For dual-slope waveform operations, the update time occurs when the counter reaches ZERO. For the other waveforms generation modes, the update time occurs on counter wraparound, on overflow, underflow, or re-trigger.

The table below shows the update counter and overflow event/interrupt generation conditions in different operation modes.

Table 35-2. Counter Update and Overflow Event/interrupt Conditions
Name Operation TOP Update Output Waveform OVFIF/Event
On Match On Update Up Down
NFRQ Normal Frequency PER TOP/ ZERO Toggle Stable TOP ZERO
MFRQ Match Frequency CC0 TOP/ ZERO Toggle Stable TOP ZERO
NPWM Single-slope PWM PER TOP/ ZERO See section 'Output Polarity' below TOP ZERO
DSCRITICAL Dual-slope PWM PER ZERO - ZERO
DSBOTTOM Dual-slope PWM PER ZERO - ZERO
DSBOTH Dual-slope PWM PER TOP(1) & ZERO TOP ZERO
DSTOP Dual-slope PWM PER ZERO TOP –
  1. The UPDATE condition on TOP only will occur when circular buffer is enabled for the channel.