22.6.1.5 Sleep Mode Operation
In Standby mode, the low-power voltage regulator (LPVREG) is used to supply VDDCORE.
When the Run in Standby bit in the VREG register (VREG.RUNSTDBY) is written to '1', VDDCORE is supplied by the main voltage regulator. Depending on the Standby in PL0 bit in the Voltage Regulator register (VREG.STDBYPL0), the VDDCORE level is either set to the PL0 voltage level, or remains in the current performance level.
| VREG.RUNSTDBY | VREG.STDBYPL0 | VDDCORE Supply in Standby Mode |
|---|---|---|
| 0 | - | LPVREG |
| 1 | 0 | MAINVREG in current performance level(1) |
| 1 | 1 | MAINVREG in PL0 |
- When the device is in PL0 but VREG.STDBYPL0 = 0, the MAINVREG is operating in normal power mode. To minimize power consumption, operate MAINVREG in PL0 mode by selecting VREG.STDBYPL0 = 1.
By writing the Low-Power mode Efficiency bit in the VREG register (VREG.LPEFF) to '1', the efficiency of the regulator in LPVREG can be improved when the application uses a limited VDD range (2.5 to 3.6V). It is also possible to use the BOD33 to monitor the VDD and change this LPEFF value on the fly according to VDD level.
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