26.6.25 RTC TimeStamp Source Register 1

This register is cleared after read, and the read access also performs a clear on RTC_TSTR1 and RTC_TSDR1.

The following configuration values are valid for all listed bit names of this register:

0: No alarm generated since the last clear of this register.

1: An alarm has been generated by the corresponding monitor since the last read of this register.

Name: RTC_TSSR1
Offset: 0xC4
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 DET7DET6DET5DET4DET3DET2DET1DET0 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
     JTAGTST   
Access RR 
Reset 00 

Bits 16, 17, 18, 19, 20, 21, 22, 23 – DETx PIOBU Intrusion Detector (cleared on read)

Bit 3 – JTAG JTAG Pins Monitor (cleared on read)

Bit 2 – TST Test Pin Monitor (cleared on read)