33.7.32 Secure PIO Write Protection Status Register
| Name: | S_PIO_WPSR |
| Offset: | 0x15E4 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WPVSRC[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WPVSRC[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| NCE | WPVS | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
Bits 23:8 – WPVSRC[15:0] Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
Bit 4 – NCE Non-Correctable Error on Configuration Registers (cleared on read)
| Value | Description |
|---|---|
| 0 | No single error has been detected in the PIO_CFGR/IMR/EIMR/ODSR/IOSSR registers since the last read of S_PIO_WPSR. |
| 1 | A non-correctable error has been detected in the PIO_CFGR/IMR/ODR registers since the last read of S_PIO_WPSR. This flag is set under abnormal operating conditions, or if a fault injection is performed. The error is not corrected and the software must reconfigure the relevant configuration registers. This is the same flag as PIO_WPSR.NCE. The clear is performed if the source of error has disappeared. |
Bit 0 – WPVS Write Protection Violation Status
| Value | Description |
|---|---|
| 0 | No write protection violation has occurred since the last read of the S_PIO_WPSR. |
| 1 | A write protection violation has occurred since the last read of the S_PIO_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. |