32.7 Programmable Clock Controller

The PMC controls three signals to be outputs on external pins PCKx. Each signal can be independently programmed via the Programmable Clock registers (PMC_PCKx).

PCKx can be independently selected between the Slow clock (TD_SLCK), the Main System Bus clock (MCK), the PLLACK, the UTMI PLL output, the Main clock and the AUDIO PLL (AUDIOPLLCLK) output by writing PMC_PCKx.CSS. Each output signal can also be divided by a factor between 1 and 256 by writing PMC_PCKx.PRES.

Each output signal can be enabled and disabled by writing a ‘1’ in the corresponding bits, PMC_SCER.PCKx and PMC_SCDR.PCKx, respectively. The status of each active programmable output clocks is given in PMC_SCSR.PCKx.

The status flag PMC_SR.PCKRDYx indicates that the Programmable clock programmed in PMC_PCKx is ready.

As the Programmable Clock Controller does not implement glitch prevention when switching clocks, the PCKx must be disabled before any configuration change (clock source and prescaler) and must be re-enabled after the change is performed.