8.2.4.1 DDR I/O Calibration

The DDR2/DDR3/LPDDR1/LPDDR2/LPDDR3/DDR3L I/Os embed an automatic impedance matching control to avoid overshoots and reach the best performance levels depending on the bus load and external memories. A serial termination connection scheme, where the driver has an output impedance matched to the characteristic impedance of the line, is used to improve signal quality and reduce EMI.

One specific analog input, DDR_CAL, is used to calibrate all DDR / IOs.

The MPDDRC supports the ZQ calibration procedure used to calibrate the device’s DDR I/O drive strength and the commands to setup the external DDR device drive strength (refer to the section Multiport DDR-SDRAM Controller (MPDDRC)). The calibration cell supports all the memory types listed above.

Figure 8-2. DDR Calibration Cell

The calibration cell provides an input pin, DDR_CAL, loaded with one of the following resistor RZQ values:

  • 24 KΩ for LPDDR2/LPDDR3
  • 23 KΩ for DDR3L
  • 22 KΩ for DDR3
  • 21 KΩ for DDR2/LPDDR1

The typical value for CZQ is 22 pF.