28.5.1 Slow Clock Controller Configuration Register

Name: SCKC_CR
Offset: 0x0
Reset: 0x00000001
Property: Read/Write

This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register (SYSC_WPMR).

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
     OSCSEL    
Access R/W 
Reset 0 

Bit 3 – OSCSEL Slow Clock Selector

ValueDescription
0 (RC) The slow clock is the embedded always-on 64 kHz (typical) RC oscillator.
1 (XTAL) The slow clock is the 32.768 kHz crystal oscillator.