13.6.2.1 Memory Types
Although various different memory types can be specified in the page tables, the Cortex-A5 processor does not implement all possible combinations:
- Write-through caches are not supported. Any memory marked as write-through is treated as Non-cacheable.
- The outer shareable attribute is not supported. Anything marked as outer shareable is treated in the same way as inner shareable.
- Write-back no write-allocate is not supported. It is treated as write-back write-allocate.
The table below shows the treatment of each different memory type in the Cortex-A5 processor in addition to the architectural requirements.
| Memory Type Attribute | Shareability | Other Attributes | Notes |
|---|---|---|---|
| Strongly Ordered | – | – | – |
| Device | Non-shareable | – | – |
| Shareable | – | – | |
| Normal | Non-shareable | Non-cacheable | Does not access L1 caches |
| Write-through cacheable | Treated as non-cacheable | ||
| Write-back cacheable, write allocate | Can dynamically switch to no write allocate, if more than three full cache lines are written in succession | ||
| Write-back cacheable, no write allocate | Treated as non-shareable write-back cacheable, write allocate | ||
| Inner shareable | Non-cacheable | – | |
| Write-through cacheable | Treated as inner shareable non-cacheable | ||
| Write-back cacheable, write allocate | Treated as inner shareable non-cacheable unless the SMP bit in the Auxiliary Control Register is set (ACTLR[6] = b1). If this bit is set the area is treated as write-back cacheable write allocate. | ||
| Write-back cacheable, no write allocate | |||
| Outer shareable | Non-cacheable | Treated as inner shareable non-cacheable | |
| Write-through cacheable | |||
| Write-back cacheable, write allocate | Treated as inner shareable non-cacheable unless the SMP bit in the Auxiliary Control Register is set (ACTLR[6] = b1). If this bit is set the area is treated as write-back cacheable write allocate. | ||
| Write-back cacheable, no write allocate |