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Ultra-Low-Power Arm® Cortex®-A5 Core-Based MPU, 500 MHz, Graphics Interface, Ethernet 10/100, CAN, USB, PCI 5.0 Pre-Certified SAMA5D2 Series
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39
Ethernet MAC (GMAC)
39.6
Functional Description
39.6.5
Transmit Scheduling Algorithm
SAMA5D2 Series
Introduction
Features
Description
1
Configuration Summary
2
Block Diagram
3
Signal Description
4
Microchip Recommended Power Management Solutions
5
Safety and Security Features
6
Package and Pinout
7
Power Considerations
8
Memories
9
Event System
10
System Controller
11
Peripherals
12
Chip Identifier (CHIPID)
13
Cortex-A5 Processor (ARM)
14
L2 Cache Controller (L2CC)
15
Debug and Test Features
16
Standard Boot Strategies
17
CPU System Bus Matrix (CPUMX)
18
Matrix (H64MX/H32MX)
19
Special Function Registers (SFR)
20
Special Function Registers Backup (SFRBU)
21
Advanced Interrupt Controller (AIC)
22
Watchdog Timer (WDT)
23
Reset Controller (RSTC)
24
Shutdown Controller (SHDWC)
25
Periodic Interval Timer (PIT)
26
Real-time Clock (RTC)
27
System Controller Write Protection (SYSCWP)
28
Slow Clock Controller (SCKC)
29
Peripheral Touch Controller (PTC)
30
Low Power Asynchronous Receiver (RXLP)
31
Clock Generator
32
Power Management Controller (PMC)
33
Parallel Input/Output Controller (PIO)
34
External Memories
35
DDR-SDRAM Controller (MPDDRC)
36
Static Memory Controller (SMC)
37
DMA Controller (XDMAC)
38
LCD Controller (LCDC)
39
Ethernet MAC (GMAC)
39.1
Description
39.2
Embedded Characteristics
39.3
Block Diagram
39.4
Signal Interfaces
39.5
Product Dependencies
39.6
Functional Description
39.6.1
Media Access Controller
39.6.2
1588 Timestamp Unit
39.6.3
Direct Memory Access Interface
39.6.4
MAC Transmit Block
39.6.5
Transmit Scheduling Algorithm
39.6.5.1
Introduction
39.6.5.2
802.1Qav Support - Credit-based Shaping
39.6.5.3
Fixed Priority
39.6.5.4
Deficit Weighted Round Robin (DWRR)
39.6.5.5
Enhanced Transmission Selection (ETS)
39.6.6
MAC Receive Block
39.6.7
Checksum Offload for IP, TCP and UDP
39.6.8
MAC Filtering Block
39.6.9
Broadcast Address
39.6.10
Hash Addressing
39.6.11
Copy all Frames (Promiscuous Mode)
39.6.12
Disable Copy of Pause Frames
39.6.13
VLAN Support
39.6.14
Wake on LAN Support
39.6.15
IEEE 1588 Support
39.6.16
MAC 802.3 Pause Frame Support
39.6.17
MAC PFC Priority-based Pause Frame Support
39.6.18
Energy-efficient Ethernet Support
39.6.19
LPI Operation in the GMAC
39.6.20
PHY Interface
39.6.21
10/100 Operation
39.6.22
Jumbo Frames
39.7
Programming Interface
39
Register Summary
40
USB Device High Speed Port (UDPHS)
41
USB Host High Speed Port (UHPHS)
42
Audio Class D Amplifier (CLASSD)
43
Inter-IC Sound Controller (I2SC)
44
Synchronous Serial Controller (SSC)
45
Two-wire Interface (TWIHS)
46
Flexible Serial Communication Controller (FLEXCOM)
47
Universal Asynchronous Receiver Transmitter (UART)
48
Serial Peripheral Interface (SPI)
49
Quad Serial Peripheral Interface (QSPI)
50
Secure Digital MultiMedia Card Controller (SDMMC)
51
Image Sensor Controller (ISC)
52
Controller Area Network (MCAN)
53
Timer Counter (TC)
54
Pulse Density Modulation Interface Controller (PDMIC)
55
Pulse Width Modulation Controller (PWM)
56
Secure Fuse Controller (SFC)
57
Integrity Check Monitor (ICM)
58
Advanced Encryption Standard Bridge (AESB)
59
Advanced Encryption Standard (AES)
60
Secure Hash Algorithm (SHA)
61
Triple Data Encryption Standard (TDES)
62
True Random Number Generator (TRNG)
63
Analog Comparator Controller (ACC)
64
Security Module (SECUMOD)
65
Analog-to-Digital Controller (ADC)
66
Electrical Characteristics
67
Mechanical Characteristics
68
Marking
69
Ordering Information
70
Revision History
Microchip Information
39.6.5 Transmit Scheduling Algorithm
