32.22.1 PMC System Clock Enable Register

This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.

Name: PMC_SCER
Offset: 0x0000
Reset: –
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
      ISCCK   
Access W 
Reset – 
Bit 15141312111098 
      PCK2PCK1PCK0 
Access WWW 
Reset ––– 
Bit 76543210 
 UDPUHP  LCDCKDDRCK   
Access WWWW 
Reset –––– 

Bit 18 – ISCCK ISC Clock Enable

ValueDescription
0

No effect.
1

Enables the ISC clock.

Bits 8, 9, 10 – PCKx Programmable Clock x Output Enable

ValueDescription
0

No effect.
1

Enables the corresponding Programmable Clock output.

Bit 7 – UDP USB Device Clock Enable

ValueDescription
0

No effect.
1

Enables the USB Device clock.

Bit 6 – UHP USB Host OHCI Clocks Enable

ValueDescription
0

No effect.
1

Enables the UHP48M and UHP12M OHCI clocks.

Bit 3 – LCDCK MCK2x Clock Enable

MCK2x is selected as LCD Pixel source clock if LCDC_LCDCFG0.CLKSEL = 1.
ValueDescription
0

No effect.
1

Enables the MCK2x clock.

Bit 2 – DDRCK DDR Clock Enable

ValueDescription
0

No effect.
1

Enables the DDR clock.