14.5.2 L2CC Type Register
| Name: | L2CC_TYPR |
| Offset: | 0x004 |
| Reset: | 0x00100100 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DL2WSIZE[2:0] | DL2ASS | ||||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 1 | 0 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| IL2WSIZE[2:0] | |||||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 1 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IL2ASS | |||||||||
| Access | R | ||||||||
| Reset | 0 |
Bits 22:20 – DL2WSIZE[2:0] Data L2 Cache Way Size
The value is read from the field WAYSIZE in Auxiliary Control Register, should be 0x1.
Bit 18 – DL2ASS Data L2 Cache Associativity
The value is read from the field ASS in Auxiliary Control Register, should be 0.
Bits 10:8 – IL2WSIZE[2:0] Instruction L2 Cache Way Size
The value is read from the field WAYSIZE in Auxiliary Control Register, should be 0x1.
Bit 6 – IL2ASS Instruction L2 Cache Associativity
The value is read from the field ASS in Auxiliary Control Register, should be 0.