14.5.27 L2CC Debug Control Register
| Name: | L2CC_DCR |
| Offset: | 0xF40 |
| Reset: | 0x00000000 |
| Property: | Read/Write in Secure mode, Read-only in Non-secure mode |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SPNIDEN | DWB | DCL | |||||||
| Access | |||||||||
| Reset | 0 | 0 | 0 |
Bit 2 – SPNIDEN SPNIDEN Value
Bit 1 – DWB Disable Write-back, Force Write-through
| Value | Description |
|---|---|
| 0 | Enables write-back behavior. This is the default value. |
| 1 | Forces write-through behavior. |
Bit 0 – DCL Disable Cache Linefill
| Value | Description |
|---|---|
| 0 | Enables cache linefills. This is the default value. |
| 1 | Disables cache linefills. |