2.4 Configuration Bytes

The devices have 13 Configuration Bytes, starting at address 0x300000. The Configuration bits enable or disable specific features, placing these controls outside the normal software process, and they establish configured values prior to the execution of any software.
Important:

The address location for the Configuration bytes on these devices does not increment sequentially. Refer to the Register Summary for address locations.

In terms of programming, consider the following Configuration bits:
  1. SAFLOCK: Storage Area Flash (SAF) Lock Enable bit(1)
    • 1 = OFF: SAF Lock disabled.
    • 0 = ON: SAF Lock enabled; SAF areas are locked, SAFSZ bits can only be set to '0' but cannot be erased to '1'.
  2. ICSPDIS: Programming and Debugging Interface Disable (PDID) bit(2)
    • 1 = OFF: ICSP and debugging interface fully enabled.
    • 0 = ON: ICSP and debugging interface fully disabled.
  3. LVP: Low-Voltage Programming Enable bit
    • 1 = ON: Low-Voltage Programming is enabled. MCLR/VPP pin function is MCLR. The MCLRE Configuration bit is ignored.
    • 0 = OFF: High voltage on MCLR/VPP must be used for programming.
    Important: The LVP bit cannot be written (to ‘0’) while operating from the LVP programming interface. The purpose of this rule is to prevent the user from dropping out of LVP mode while programming from LVP mode or accidentally eliminating LVP mode from the Configuration state. For more information, refer to Low-Voltage Programming (LVP) Mode.
  4. MCLRE: Master Clear (MCLR) Enable bit
    • If LVP = 1: RE3 pin function is MCLR
    • If LVP = 0
      • 1 = RE3 pin is MCLR
      • 0 = RE3 pin function is a port-defined function
  5. CP: User Program Flash Memory (PFM) Program Memory Code Protection bit
    • 1 = OFF: User PFM code protection is disabled
    • 0 = ON: User PFM code protection is enabled
  6. CPD: Data EEPROM Code Protection bit
    • 1 = OFF: Data EEPROM code protection is disabled
    • 0 = ON: Data EEPROM code protection is enabled

For more information on code protection, see the Enhanced Code Protection section.

CAUTION:
  1. Once enabled, the SAFLOCK bit cannot be disabled. Bulk Erase and self-erase operations of the SAFLOCK bit and the selected SAF region are not possible. Refer to the Storage Area Flash (SAF) Lock Enable section for more information.
  2. Once enabled, the ICSPDIS bit cannot be disabled (even through a Bulk Erase operation) and the Programming and Debugging Interface is completely disabled. Refer to the PDID section for more information about the PDID feature.