5.5 Ethernet PHY
The Microchip SAMA5D27 SOM1 embeds a single-supply 10BASE-T/100BASE-TX Ethernet physical-layer transceiver for transmission and reception of data over standard CAT-5 unshielded twisted pair (UTP) cable.
The KSZ8081RNAIA is a highly-integrated PHY solution. The KSZ8081RNAIA offers the Reduced Media Independent Interface (RMII) for direct connection to RMII-compliant MACs in Ethernet processors.
The KSZ8081RNAIA is available in 24-pin, lead-free QFN packages. For more information, refer to the product web page.
| Power Rail | I/O Type | Primary | Alternate | PIO Peripheral | Reset State | Note | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| Signal | Type | Signal | Dir | Func | Signal | Dir | IO Set | Signal, Dir, PU, PD, HiZ, ST, SEC, FILTER | |||
| VDDIN_3V3 | GPIO | PD9 | I/O | – | – | D | GTXCK | O | 2 | PIO, I, PU, ST | Used for RMII Interface |
| VDDIN_3V3 | GPIO | PD10 | I/O | – | – | D | GTXEN | O | 2 | PIO, I, PU, ST | |
| VDDIN_3V3 | GPIO | PD11 | I/O | – | – | D | GRXDV | I | 2 | PIO, I, PU, ST | |
| VDDIN_3V3 | GPIO | PD12 | I/O | – | – | D | GRXER | I | 2 | PIO, I, PU, ST | |
| VDDIN_3V3 | GPIO | PD13 | I/O | – | – | D | GRX0 | I | 2 | PIO, I, PU, ST | |
| VDDIN_3V3 | GPIO | PD14 | I/O | – | – | D | GRX1 | I | 2 | PIO, I, PU, ST | |
| VDDIN_3V3 | GPIO | PD15 | I/O | – | – | D | GTX0 | O | 2 | PIO, I, PU, ST | |
| VDDIN_3V3 | GPIO | PD16 | I/O | – | – | D | GTX1 | O | 2 | PIO, I, PU, ST | |
| VDDIN_3V3 | GPIO | PD17 | I/O | – | – | D | GMDC | O | 2 | PIO, I, PU, ST | Used for MDIO Interface |
| VDDIN_3V3 | GPIO | PD18 | I/O | – | – | D | GMDIO | I/O | 2 | PIO, I, PU, ST | |
| VDDIN_3V3 | GPIO | PD31 | I/O | – | – | – | PB24 | -- | -- | PIO, I, PU, ST | Interrupt Line |