13.12.7 SCANCON0

Scanner Access Control Register 0
Note:
  1. Setting EN = 0 does not affect any other register content.
  2. Scanner trigger selection can be set using SCANTRIG register.
  3. This bit can be cleared in software. It is cleared in hardware when LADR > HADR (and a data cycle is not occurring) or when CRCGO = 0.
  4. CRCEN and CRCGO bits must be set before setting the SGO bit.
  5. Refer to Scanning Modes.
Name: SCANCON0
Address: 0x360

Bit 76543210 
 ENTRIGENSGO  MREGBURSTMDBUSY 
Access R/WR/WR/W/HCR/WR/WR/W 
Reset 000000 

Bit 7 – EN  Scanner Enable(1)

ValueDescription
1Scanner is enabled
0Scanner is disabled

Bit 6 – TRIGEN  Scanner Trigger Enable(2,5)

ValueDescription
1Scanner trigger is enabled
0Scanner trigger is disabled

Bit 5 – SGO  Scanner GO(3,4)

ValueDescription
1When the CRC is ready, the Memory region set by the MREG bit will be accessed and data are passed to the CRC peripheral.
0Scanner operations will not occur

Bit 2 – MREG  Scanner Memory Region Select(2)

ValueDescription
1Scanner address points to Data EEPROM
0Scanner address points to Program Flash Memory

Bit 1 – BURSTMD  Scanner Burst Mode(5)

ValueDescription
1Memory access request to the CPU Arbiter is always true
0Memory access request to the CPU Arbiter is dependent on the CRC request and Trigger

Bit 0 – BUSY Scanner Busy Indicator

ValueDescription
1Scanner cycle is in process
0Scanner cycle is compete (or never started)
Setting EN Scanner Enable(1) = 0 does not affect any other register content.Scanner trigger selection can be set using SCANTRIG register.This bit can be cleared in software. It is cleared in hardware when LADR > HADR (and a data cycle is not occurring) or when CRCGOCRC Start = 0.CRCENCRC Enable and CRCGOCRC Start bits must be set before setting the SGO bit.Refer to Scanning Modes.