25.2.3.6.2 7-bit Reception with AHEN and DHEN
Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the eighth falling edge of SCL. These additional interrupts allow the slave software to decide whether it wants to ACK the receive address or data byte, rather than the hardware. This functionality adds support for PMBus™ that was not present on previous versions of this module.
This list describes the steps that need to be taken by slave software to use these options for I2C communication. Figure 25-18 displays a module using both address and data holding. Figure 25-19 includes the operation with the SEN bit set.
- The Start (S) bit is set; SSPxIF is set if SCIE is set.
- Matching address with the R/W bit clear is clocked in. SSPxIF is set and CKP cleared after the eighth falling edge of SCL.
- Software clears the SSPxIF.
- Slave can look at the ACKTIM bit to determine if the SSPxIF was after or before the ACK.
- Slave reads the address value from SSPxBUF, clearing the BF flag.
- Slave transmits an ACK to the master by clearing ACKDT.
- Slave releases the clock by setting CKP.
- SSPxIF is set after an ACK, not after a NACK.
- If SEN =
1
, the slave hardware will stretch the clock after the ACK. - Slave clears SSPxIF.Important: SSPxIF is still set after the ninth falling edge of SCL even if there is no clock stretching and BF has been cleared. Only if a NACK is sent to the master is SSPxIF not set.
- SSPxIF is set and CKP cleared after eighth falling edge of SCL for a received data byte.
- Slave looks at the ACKTIM bit to determine the source of the interrupt.
- Slave reads the received data from SSPxBUF, clearing BF.
- Steps 7-14 are the same for each received data byte.
- Communication is ended by either the slave sending a NACK, or the master sending a Stop condition. If a Stop is sent and the Stop Condition Interrupt Enable (PCIE) bit is clear, the slave will only know by polling the Stop (P) bit.