20.11.3 TxCLK

Timer Clock Source Selection Register

Name:	TxCLK
Address:	0x211


Bit	7	6	5	4	3	2	1	0
				CS[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 4:0 – CS[4:0] Timer Clock Source Selection

Table 20-4. Timer Clock Sources
CS	Clock Source
`11111-01001`	Reserved
`01000`	TMR0_OUT
`00111`	MFINTOSC (32 kHz)
`00110`	MFINTOSC (500 kHz)
`00101`	SFINTOSC (1 MHz)
`00100`	LFINTOSC
`00011`	HFINTOSC
`00010`	F_OSC
`00001`	F_OSC/4
`00000`	Pin selected by T1CKIPPS

Reset States:

POR/BOR = 00000

All Other Resets = uuuuu

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