3.1 Supply Current Profile
The supply current profile for a complete Verifier operation including power-up, initialization, calibration of the Verifier offset mode with Prover response and power-down is shown in Figure 3-1, Figure 3-2 and Figure 3-3. The figures show the analog signals, VDD_CORE (supply voltage for the core), IDD_CORE (supply current for the core) at 1.25V and IDD_SUP at 3.3V (supply domain), and the digital signals, N_RST, 1V2_ENA, SPI_CE, IRQ and Controller state signals. The complete sequence of operations requires ~7.6 ms. The measurement was performed with the evaluation kit using a SAMC21 MCU with 48 MHz clock and an SPI communication with an 8 MHz clock frequency. The supply current (IDD_SUP) includes the current for the VDD_IO domain and the current for a DC/DC converter to supply the VDD_CORE domain (the DC/DC converter used for the measurement is TPS62244-Q1 with a 1.25V output voltage).
Following is the sequence operation:
- The DC/DC is switched On at -7.1 ms when the signal, 1V2_ENA, is set to high and, after 1 ms, release the N_RST signal.
- Switch On the crystal oscillator at -5.8 ms.
- Load the device registers.
- Initialize the PLL at -3.7 ms and the calibration of the FLL RX at -3.2 ms.
- Set the RF RX and TX frequencies at -1.7 ms, and enter the READY mode at -1.0 ms.