3.2 Verifier Mode Current Consumption

The Verifier mode, VRo, is started with the transmission state and the controller state at 1101 (for details, refer to the ATA8352 User Manual). See the following figure. The turnaround phases follow this and receive a locked state at 0110. The IRQ signal is activated when the receive is complete and the registers are read. Enable the reset signal (N_RST) to start the power-down sequence and disable the DC/DC converter.

Figure 3-1. Current Profile for Verifier Operation

The following figure (zoomed in from -2.0 to 2.0 ms) shows the Verifier operation in VRo mode.

Figure 3-2. Current Profile for the Verifier Mode VRo