Measuring Power in Active and Low Power Mode

The Power Graph tab can be used to observe the FPGA Core Power (W) and initiate Flash Freeze.

To observe the FPGA Core Power (W) and initiate Flash Freeze, perform the following steps:
  1. In the Flash Freeze pane, click Flash Freeze Entry to switch the FPGA from Functional mode to Low Power mode and observe the power drop in the GUI.
    Figure . Power Drop
  2. Click the Flash Freeze Exit to switch the FPGA back to Functional mode. The time to exit Flash Freeze mode can be observed in the Flash Freeze pane.
    Figure . Serial Terminal
    Note: Each demo that comes with the GUI is identified by the design version set in the dat file. Version numbers 4,6, and 7 are reserved. User must not use these design version numbers during dat file generation for their custom designs. GUI reads the current design version on the kit and loads the appropriate FPGA demo on a successful connection. For custom designs, a generic ‘Serial Terminal’ is loaded instead of FPGA demo. This tab enables the user to communicate to the FPGA over Serial protocol.