17.1 PPS Inputs

Each peripheral has an xxxPPS register with which the input pin to the peripheral is selected. Not all ports are available for input as shown in the following table.

Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must be cleared to enable the digital input buffer.

Important: The notation “xxx” in the generic register name is a place holder for the peripheral identifier. For example, xxx = INT0 for the INT0PPS register.
Table 17-1. PPS Input Selection Register Details
PeripheralPPS Input RegisterDefault Pin Selection
 at PORRegister Reset Value
 at PORPORT From Which Input Is Available
28-Pin Devices40-Pin Devices
Interrupt 0INT0PPSRB00x08AB—AB——
Interrupt 1INT1PPSRB10x09AB—AB——
Interrupt 2INT2PPSRB20x0AAB—AB——
Timer0 ClockT0CKIPPSRA40x04AB—AB——
Timer1 ClockT1CKIPPSRC00x10A—CA—C—
Timer1 GateT1GPPSRB50x0D—BC—BC—
Timer3 ClockT3CKIPPSRC00x10—BC—BC—
Timer3 GateT3GPPSRC00x10A—CA—C—
Timer5 ClockT5CKIPPSRC20x12A—CA—C—
Timer5 GateT5GPPSRB40x0C—B——B—D
Timer2 ClockT2INPPSRC30x13A—CA—C—
Timer4 ClockT4INPPSRC50x15—BC—BC—
Timer6 ClockT6INPPSRB70x0F—B——B—D
ADC Conversion TriggerADACTPPSRB40x0C—BC—B—D
CCP1CCP1PPSRC20x12—BC—BC—
CCP2CCP2PPSRC10x11—BC—BC—
CWGCWG1PPSRB00x08—BC—B—D
DSM Carrier LowMDCARLPPSRA30x03A—CA——D
DSM Carrier HighMDCARHPPSRA40x04A—CA——D
DSM SourceMDSRCPPSRA50x05A—CA——D
EUSART1 ReceiveRX1PPSRC70x17—BC—BC—
EUSART1 ClockCK1PPSRC60x16—BC—BC—
EUSART2 ReceiveRX2PPSRB70x0F—BC—B—D
EUSART2 ClockCK2PPSRB60x0E—BC—B—D
MSSP1 ClockSSP1CLKPPSRC30x13—BC—BC—
MSSP1 DataSSP1DATPPSRC40x14—BC—BC—
MSSP1 Slave SelectSSP1SSPPSRA50x05A—CA——D
MSSP2 ClockSSP2CLKPPSRB10x09—BC—B—D
MSSP2 DataSSP2DATPPSRB20x0A—BC—B—D
MSSP2 Slave SelectSSP2SSPPSRB00x08—BC—B—D