1.3 Details on Individual Family Members

Devices in the PIC18(L)F26/45/46K40 family are available in 28/40/44-pin packages. The block diagram for this device is shown in Figure 1-1.

The devices have the following differences:

  1. Program Flash Memory
  2. Data Memory SRAM
  3. Data Memory EEPROM
  4. A/D channels
  5. I/O ports
  6. Enhanced USART
  7. Input Voltage Range/Power Consumption

All other features for devices in this family are identical. These are summarized in the following Device Features table.

The pinouts for all devices are listed in the pin summary tables.

Table 1-1. Device Features
FeaturesPIC18(L)F26K40PIC18(L)F45K40PIC18(L)F46K40
Program Memory (Bytes)655363276865536
Program Memory (Instructions)327681638432768
Data Memory (Bytes)372020483720
Data EEPROM Memory (Bytes)10242561024
I/O PortsA,B,C,E(1)A,B,C,D,EA,B,C,D,E
Capture/Compare/PWM Modules (CCP)222
10-Bit Pulse-Width Modulator (PWM)222
10-Bit Analog-to-Digital Module (ADC2) with Computation Accelerator4 internal

24 external

4 internal

35 external

4 internal

35 external

Packages28-pin SPDIP

28-pin SOIC

28-pin SSOP

28-pin QFN

28-pin UQFN

40-pin PDIP

40-pin UQFN

44-pin QFN

44-pin TQFP

40-pin PDIP

40-pin UQFN

44-pin QFN

44-pin TQFP

Interrupt Sources36
Timers (16-/8-bit)4/3
Serial Communications2 MSSP,

2 EUSART

Enhanced Complementary Waveform Generator (ECWG)1
Zero-Cross Detect (ZCD)1
Data Signal Modulator (DSM)1
Peripheral Pin Select (PPS)Yes
Peripheral Module Disable (PMD)Yes
16-bit CRC with NVMSCANYes
Programmable High/Low-Voltage Detect (HLVD)Yes
Programmable Brown-out Reset (BOR)Yes
Resets (and Delays)POR, BOR,

RESET Instruction,

Stack Overflow,

Stack Underflow,

MCLR, WWDT,

(PWRT, OST)

Instruction Set75 Instructions;

83 with Extended Instruction Set enabled

Operating FrequencyDC – 64 MHz
Note 1: RE3 is an input only pin.
Figure 1-1. PIC18(L)F26/45/46K40 Family Block Diagram