27.5 Register Summary - EUSART
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
0x00 ... 0x0E98 | Reserved | |||||||||
| 0x0E99 | RC2REG | 7:0 | RCREG[7:0] | |||||||
| 0x0E9A | TX2REG | 7:0 | TXREG[7:0] | |||||||
| 0x0E9B | SP2BRG | 7:0 | SPBRGL[7:0] | |||||||
| 15:8 | SPBRGH[7:0] | |||||||||
| 0x0E9D | RC2STA | 7:0 | SPEN | RX9 | SREN | CREN | ADDEN | FERR | OERR | RX9D |
| 0x0E9E | TX2STA | 7:0 | CSRC | TX9 | TXEN | SYNC | SENDB | BRGH | TRMT | TX9D |
| 0x0E9F | BAUD2CON | 7:0 | ABDOVF | RCIDL | SCKP | BRG16 | WUE | ABDEN | ||
0x0EA0 ... 0x0F98 | Reserved | |||||||||
| 0x0F99 | RC1REG | 7:0 | RCREG[7:0] | |||||||
| 0x0F9A | TX1REG | 7:0 | TXREG[7:0] | |||||||
| 0x0F9B | SP1BRG | 7:0 | SPBRGL[7:0] | |||||||
| 15:8 | SPBRGH[7:0] | |||||||||
| 0x0F9D | RC1STA | 7:0 | SPEN | RX9 | SREN | CREN | ADDEN | FERR | OERR | RX9D |
| 0x0F9E | TX1STA | 7:0 | CSRC | TX9 | TXEN | SYNC | SENDB | BRGH | TRMT | TX9D |
| 0x0F9F | BAUD1CON | 7:0 | ABDOVF | RCIDL | SCKP | BRG16 | WUE | ABDEN | ||