32.4.3 Acquisition Control for CVD (ADPRE > 0)

The Acquisition stage allows time for the voltage on the internal Sample-and-Hold capacitor to charge or discharge from the selected analog channel. This acquisition time is controlled by the ADACQ register. When ADPRE = 0, acquisition starts at the beginning of conversion. When ADPRE > 0, the acquisition stage begins when precharge ends.

At the start of the acquisition stage, the port pin logic of the selected analog channel is overridden to turn off the digital high/low output drivers so they do not affect the final result of the charge averaging. Also, the selected ADC channel is connected to CHOLD. This allows charge averaging to proceed between the precharged channel and the CHOLD capacitor.

Important: When ADPRE > 0 setting ADACQ to ‘0’ will set a maximum acquisition time (256 ADC clock cycles). When precharge is disabled, setting ADACQ to ‘0’ will disable hardware acquisition time control.